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dc.contributor.authorAhmad, Nen_US
dc.contributor.authorHasan, SMREZAULen_US
dc.date.available2013-03en_US
dc.date.issued2013-03en_US
dc.identifierhttps://www.hindawi.com/en_US
dc.identifierArticle ID 148518en_US
dc.identifier.citationActive and Passive Electronic Components, 2013, 2013 pp. 1 - 6 (6)en_US
dc.identifier.issn1563-5031en_US
dc.description.abstractA power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.en_US
dc.format.extent1 - 6 (6)en_US
dc.publisherHindawi Publishing Corporationen_US
dc.titleA 0.8 V 0.23 nW 1.5 ns full-swing pass-transistor XOR gate in 130 nm CMOSen_US
dc.typeJournal Article
dc.citation.volume2013en_US
dc.identifier.doi10.1155/2013/148518en_US
dc.description.confidentialfalseen_US
dc.identifier.elements-id237083
dc.relation.isPartOfActive and Passive Electronic Componentsen_US
pubs.organisational-group/Massey University
pubs.organisational-group/Massey University/College of Sciences
dc.identifier.harvestedMassey_Dark
pubs.notesNot knownen_US
dc.publisher.urihttps://www.hindawi.com/en_US
dc.subject.anzsrc0906 Electrical And Electronic Engineeringen_US


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