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    Increasing the spectral efficiency of contunous phase modulation applied to digital microwave radio : a resource efficient FPGA receiver implementation : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Electronics and Computer Systems Engineering at Massey University, Palmerston North, New Zealand
    (Massey University, 2009) Bridger, Andrew B.
    In modern point to point microwave radio systems used to backhaul cellular voice and data traffic, quadrature amplitude modulation (QAM) is the norm. These systems require a highly linear power amplifier which is expensive and has relatively low power efficiency. Recently, continuous phase modulation (CPM) has been deployed in this market. The CPM transmitted waveform has a constant envelope and so a non-linear RF power amplifier can be used. This significantly reduces cost and improves power efficiency. Two important disadvantages of CPM are receiver complexity and inferior spectral efficiency compared to QAM. This thesis demonstrates a 50% spectral efficiency improvement over an existing CPM configuration without loss of detection efficiency. This is achieved by moving to coherent demodulation and extending the duration of the CPM phase pulse to 3 symbol periods. This new CPM configuration of h=1/4, M=4, L=3, is evaluated against ETSI requirements for a 28 MHz channel carrying 24 E1 circuits. Simulation of the receiver floating point model demonstrates all requirements are met. The detection efficiency requirement is exceeded by 4.7 dB. Carrier recovery, phase and timing synchronisation are assumed to be ideal. The 50% increased symbol rate, coherent reception and a longer smoother phase pulse, conspire to increase receiver complexity substantially. The Viterbi algorithm is used to perform maximum-likelihood detection resulting in a 128 state trellis. This application has a stringent cost requirement that limits the implementation target to a Field Programmable Gate Array (FPGA) costing less than US$30. To demonstrate this demanding cost target is met, the two most computationally expensive receiver functions, the branch metric unit and path metric processing unit, are implemented in VHDL and targeted to a Xilinx Spartan 3A-DSP 1800 FPGA. The implementation uses 67% of the available logic resources, thus meeting the cost requirement. The branch metric unit is implemented using a distributed arithmetic technique that performs the equivalent of 27.6 giga-multiplies/s, consuming only 23% of the available FPGA logic cells. This is very efficient compared to a conventional approach using all the FPGA’s embedded multipliers which combined can only achieve 21 giga-multiplies/s. The Viterbi path metric processing unit is implemented using a more conventional state-parallel architecture. To reduce state metric routing complexity, states are grouped into radix-4 units comprising dual add-compare-select (ACS) units. By utilising a spare cycle in the deep ACS pipeline, each ACS unit processes two output state metrics, thus halving the number of ACS units required. This implementation uses 44% of the available FPGA resources and meets timing at 204.5 MHz, exceeding the throughput requirement of 54 Mbit/s.
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    VERTIPH : a visual environment for real-time image processing on hardware : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Computer Systems Engineering at Massey University, Palmerston North, New Zealand
    (Massey University, 2009) Johnston, Christopher Troy
    This thesis presents VERTIPH, a visual programming language for the development of image processing algorithms on FPGA hardware. The research began with an examination of the whole design cycle, with a view to identifying requirements for implementing image processing on FPGAs. Based on this analysis, a design process was developed where a selected software algorithm is matched to a hardware architecture tailor made for its implementation. The algorithm and architecture are then transformed into an FPGA suitable design. It was found that in most cases the most efficient mapping for image processing algorithms is to use a streamed processing approach. This constrains how data is presented and requires most existing algorithms to be extensively modified. Therefore, the resultant designs are heavily streamed and pipelined. A visual notation was developed to complement this design process, as both streaming and pipelining can be well represented by data flow visual languages. The notation has three views each of which represents and supports a different part of the design process. An architecture view gives an overview of the design's main blocks and their interconnections. A computational view represents lower-level details by representing each block by a set of computational expressions and low-level controls. This includes a novel visual representation of pipelining that simplifies latency analysis, multiphase design, priming, flushing and stalling, and the detection of sequencing errors. A scheduling view adds a state machine for high-level control of processing blocks. This extended state objects to allow for the priming and flushing of pipelined operations. User evaluations of an implementation of the key parts of this language (the architecture view and the computational view) found that both were generally good visualisations and aided in design (especially the type interface, pipeline and control notations). The user evaluations provided several suggestions for the improvement of the language, and in particular the evaluators would have preferred to use the diagrams as a verification tool for a textual representation rather than as the primary data capture mechanism. A cognitive dimensions analysis showed that the language scores highly for thirteen of the twenty dimensions considered, particularly those related to making details of the design clearer to the developer.
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    GateOS : a minimalist windowing environment and operating system for FPGAs : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Computer Systems Engineering at Massey University, Palmerston North, New Zealand
    (Massey University, 2007) Buhler, Andreas
    In order to debug and tune stand-alone FPGA image processing configurations, it is necessary for a developer to also create the required debug tools and to implement them on the FPGA. This process takes both time and effort that could be better spent on improving the image processing algorithms. The Gate Array Terminal Operating System (GateOS) is proposed to relieve the developer of the need to construct many of these debugging tools. In GateOS we separate the image processing algorithms from the rest of the operating system. GateOS is presented to the developer as a Handel-C library, which can be customised at compile-time, to facilitate the creation of windows and widgets. Several types of widgets are described that can manipulate the parameters of image processing algorithms and enable the end-user to dynamically rearrange the position of a window on the VDU. An end user is able to interact with GateOS with both a keyboard and a mouse.