Massey Documents by Type

Permanent URI for this communityhttps://mro.massey.ac.nz/handle/10179/294

Browse

Subject: search.filters.subject.Integrated circuits

Search Results

Now showing 1 - 5 of 5
  • Thumbnail Image
    Item
    Integrated power amplifier and antenna-on-chip for 5G communication applications : thesis by publications presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Engineering, Massey University, Auckland, New Zealand
    (Massey University, 2023) Ali, Syed Muhammad Ammar
    With the advent of 5G cellular networks, there is a crucial requirement for wireless hardware operable at microwave and millimeter-wave (mmW) frequencies. Two significant elements of wireless hardware are Power Amplifier (PA) and Antenna. An integrated power amplifier designed for 5G communications is expected to offer maximum performance in terms of efficiency, output power, and/or gain. An On-Chip Antenna design would require features like simple geometry, a small form factor, free from the risk of micro-fracture, and cost-effectiveness. Among different classes of PAs, the Class-F-1 amplifier is selected because it offers relatively better output power and efficiency. Different techniques are utilized in this work to enhance the performance parameters of the Class-F-1 PA, designed at the 5G-millimeterwave frequency of 38-GHz. In order to achieve high gain, a two-stage topology of Class-F-1 PA is employed. For the purpose of obtaining high output power, a stacking structure is established in the final stage of the two-stage topology. Class-F-1-based parasitic-aware harmonic-control loading is employed to improve the efficiency of the power amplifier. Therefore, a two-stage Class-F-1 power amplifier with a double-stacked configuration is designed and fabricated. GlobalFoundries 8HP 130nm SiGe-BiCMOS process technology is utilized for realizing the integrated mmW power amplifier. A Figure of Merit (FoM) is calculated for comparing the performance of the designed power amplifier with other mmW amplifiers reported in the literature. It is observed that the proposed two-stage double-stacked Class-F-1 PA shows comparatively the highest FoM (69.68) achieved so far in state-of-the-art silicon-based Class F/F-1 power amplifiers. Another integrated Class-F-1 power amplifier is proposed at a new unlicensed 5G-microwave frequency of 6-GHz. The PA is designed to achieve very high power-efficiency. The amplifier employs a “single-transistor” design in 65-nm standard CMOS process technology. The PA is loaded with a Class-F-1 harmonic-control network, employing a new parasitic-aware topology deduced using a novel iterative-algorithm. The proposed algorithm starts from a specific reference value and quickly converges towards the solution. A dual-purpose output-matching circuit is employed in the design. The output-matching circuit not only matches the output impedance to 50-Ω but also reinforces the Class-F-1 harmonic network in controlling the harmonics efficiently. The proposed amplifier offers a peak power-added-efficiency (PAE) of 47.8% which is one of the highest when compared with previously reported microwave/millimeterwave PAs in CMOS and SiGe process technologies. Besides power-amplifiers, another essential part of this research is On-Chip Antenna (OCA). As millimeterwave frequencies exhibit relatively smaller wavelengths, it becomes feasible to design an antenna on a microchip using standard CMOS processes. As compared to Off-Chip Antennas, the On-Chip Antennas offer a high level of integration with RF-front-end circuitry, as well as an external interconnect-free interface and low fabrication cost. An On-Chip Planar-Inverted-F Antenna (PIFA) in TSMC 180-nm CMOS is designed to radiate at the 5G-millimeterwave frequency of 38-GHz. A PIFA is selected because it offers simple geometry, small form factor, design flexibility, and robustness. An Ultra-Thick Metal (UTM) layer in 180-nm CMOS is utilized to implement the antenna structure on the chip. To achieve better radiation performance, the OCA is positioned close to the edge of the microchip. The measurements are conducted after placing the fabricated OCA over a 3D-printed plastic-slab to minimize the reflections from the metallic-chuck of the probe-station. The fabricated OCA delivered an antenna-gain of 0.7-dBi at the millimeterwave center-frequency of 38-GHz.
  • Thumbnail Image
    Item
    Modelling, analysis and design of bioelectronic circuits in VLSI : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Electronics and Computer Engineering at Massey University, Albany, New Zealand
    (Massey University, 2015) Alam, Sadia
    Biological phenomena at the molecular level are being imitated by electronic circuits. The immense effectiveness and versatility of bioelectronic circuits have yielded multiple benefits to both the electronic, and the biological worlds. Advancement in technology is being made towards the design and implementation of these systems due to their extreme proficiency and extraordinary capabilities. Development of bioelectronic circuits is assisting researchers to gain deep insights into complex processes of life. These systems are classified into different categories depending on the various kinds and nature of the biological processes. Cytomorphic and neuromorphic circuits are two major classifications of the bioelectronic systems. Cytomorphic circuits mimic the biological processes taking place inside a living cell. Activities involved in DNA-protein interactions play a vital role for the survival of living organisms. This thesis illustrates modelling and the design of the cytomorphic circuits in VLSI representing the DNA-protein interactions at the molecular level. Electronic circuits imitating neural activities are classified as neuromorphic circuits. The significance of these bioelectronic circuits cannot be denied. Hence, an effort is made in this research to model neuron-to-neuron communication process through electronic circuit components in VLSI. For an electronic representation of these phenomena, biological to electrical analogies are determined, analysed, and modelled. Circuit design validation is accomplished by comparing the circuit results with experimentally reported biological data. The cytomorphic circuit is capable of analysing the cellular behaviour of living organisms, while the neuromorphic circuit is competent to mimic the neurological processes that are dependent on neuron-to-neuron combination such as neural DNA transcription initiation. Biological experimentation on bacteria Escherichia coli is carried out that validates that the cytomorphic VLSI circuit design is capable of predicting gene behaviour of living organisms. The neuromorphic circuit is fabricated using 0.13µm IBM CMOS technology and fabrication results are illustrated in the thesis. Electronic gene oscillators and neural DNA transcription initiation circuits are illustrated as applications of the proposed VLSI bioelectronic circuit designs.
  • Thumbnail Image
    Item
    Novel digital VLSI implementation of data encryption algorithm using nano-metric CMOS technology : a thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Engineering at Massey University, Auckland, New Zealand
    (Massey University, 2013) Ahmad, Nabihah Nornabihah
    Implementations of the Advanced Encryption Standard (AES) have rapidly grown in various applications including telecommunications, finance and networks that require a low power consumption and low cost design. Presented in this thesis is a new 8-bit stream cipher architecture core for an application specific integrated circuit AES crypto-processor. The chip area and power are optimised along with high throughput by employing circuit-level techniques, resource sharing and low supply voltage. The proposed design includes a novel S-box/ InvS-box, MixColumn/ InvMixColumn and ShiftRow/ InvShiftRow with a novel low power Exclusive OR (XOR) gate applied to all sub systems to minimise the power consumption. It is implemented in a 130nm CMOS process and supports both encryption and decryption in Electronic Codebook Mode (EBC) using 128-bit keys with a throughput of 0.05Gbit/s (at 100MHz clock). This design utilises 3152 gate equivalents, including an on-the-fly key scheduling unit along with 4.23μW/MHz power consumption. The area of the chip is 640μm×325μm (0.208 square mm), excluding the bonding pads. Compared to other 8-bit implementations, the proposed design achieves a smaller chip size along with higher throughput and lower power dissipation. This thesis also describes a new fault detection scheme for S-box/ InvS-box that is parity prediction based to protect the key from fault attacks.
  • Thumbnail Image
    Item
    VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011
    (Massey University, 2011) Khurram, Muhammad
    The wide operating bandwidth of the ultra-wideband (UWB) signal leads to new circuit design challenges and methodologies. Similar to any other RF system, the most critical component of the UWB receiver is the low noise amplifier (LNA). Contrary to the narrowband LNAs, the single-tone assumption is not valid for defining the SNR of an UWB LNA where the input signal encompasses several GHz. Defining the UWB LNA system’s SNR as the matched filter bound (MFB) is an appropriate approach to deduce its noise figure (NF). Using this approach, a mathematical model is proposed to achieve optimal NF, employing the gm-boosted common gate (CG) LNA topology along with a passive noise matching input network. Besides the low noise performance, the other challenges in the design of the UWB LNA include adequate input match and forward power gain with low power dissipation. Considering the superior performance of the gm-boosted CG amplifier topology for UWB, a new single-ended (SE) gm-boosted CG UWB LNA architecture is proposed in this research. In the SE LNA architecture, the power dissipation is further minimized by sharing the bias current between the gm-boosted CG and the active gmboosting amplifier stages in a current-reuse fashion (“piggyback” gm-boosting). The proposed piggyback gm-boosted CG LNA, operating in 3-5 GHz range, is fabricated using 130nm RFCMOS process with adequate results. The noise optimization mathematical model proposed in this thesis is applied to the new piggyback gm-boosted CG LNA architecture by including an intervening noise matching passive network at the input of the LNA. The bandwidth of the noise matched piggyback gm-boosted CG LNA is extended using series peaking technique to the complete UWB band from 3.1 to 10.6 GHz. The proposed full-band noise matched UWB LNA is fabricated in a differential manner using 130nm RFCMOS process and exhibited excellent performance improvements with figure of merit (FOM) of 2.86.
  • Thumbnail Image
    Item
    A two-dimensional extensible bus technology and protocol for VLSI processor core : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Computer and Electronic Engineering at School of Engineering and Advanced Technology, Massey University, Albany, New Zealand
    (Massey University, 2011) Loke, Chun Eng
    Intellectual property (IP) core design modularity and reuse in Very-Large-Scale-Integration (VLSI) silicon have been the key focus areas in design productivity improvement in order to shorten product development lead time as well as minimize design error on new product [11]. The System-On-Chip (SoC) design approach has been adopted in microprocessor design flow with many functional blocks reuse in silicon. SoC has the advantage of cost efficiency and higher fabrication yield. The fundamental building block of SoC is the interconnection of intellectual property (IP) core through a shared bus to establish an on-chip communication. As IP core integration is severely constraint by silicon wafer sizes (cost per die), the right level of integration is never an easy decision. System-in-Package (SiP) addresses this drawback with package level IP core integration. However, SiP has the drawback of lower fabrication yield which results in higher manufacturing cost [6]. In order to address these issues, a new level of integration has been suggested in order to reduce the drawbacks of SiP and SoC approaches. This new integration methodology is also known as System-in-System (SiS) which emulates SoC and SiP at the system level. The thesis contains a detailed treatment on the processor architecture and SoC used. The design methodologies have been discussed too. The thesis also contains treatment on the verification methodologies and technologies that are used in design validation. Research includes the design of two dimensional XBUS system for external IP core integration on SoC. The thesis proposed a system level bus for IP integration through the XBUS. As there are multiple ways of integrating IP core at the system level, the XBUS is limited to two channels (hence two dimensional) in order to simplify implementation complexities. Based on experimental results, the proposed method can be introduced as a very promising method for the design of SoC and various other high-performance computer systems.