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    Piezoelectric micro-energy harvester integrated with CMOS energy extraction circuits : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Engineering at Massey University, Auckland, New Zealand. EMBARGOED until 5 November 2027.
    (Massey University, 2024-10-29) Elamana Marakkadath, Dalin
    Conventional pressure monitoring sensors used in biomedical applications, such as blood pressure and left ventricular systolic pressure measurements, have significant drawbacks, including high power consumption that shortens battery life and contributes to increased costs. A multifunctional piezoelectric transducer has been implemented for self-powered pressure sensing and energy harvesting (EH), eliminating the need for a separate transducer for pressure sensing and energy harvesting. This approach optimizes resources and reduces costs. The piezoelectric EH/sensor uses a lead-free, biocompatible, high-performance aluminum nitride (AlN) transducer. This article presents comprehensive physics-based mathematical modelling and numerical simulations that deliver optimized design parameters for a novel piezoelectric thin-film MEMS transducer energy-converter for improved pressure sensitivity and power density. The experimental results show a sensitivity of 0.06 V/kPa and a power density of 1.1 mW/cm³.--Shortened abstract
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    A 6 GHz Integrated High-Efficiency Class-F−1 Power Amplifier in 65 nm CMOS Achieving 47.8% Peak PAE
    (MDPI (Basel, Switzerland), 2021-10-09) Ali SMA; Hasan SMR; Ebrahimi A
    This paper reports a “single-transistor” Class-F−1 power amplifier (PA) in 65 nm CMOS, which operates at the microwave center frequency of 6 GHz. The PA is loaded with a Class-F−1 harmonic control network, employing a new “parasitic-aware” topology deduced using a novel iterative algorithm. A dual-purpose output matching network is designed, which not only serves the purpose of output impedance matching, but also reinforces the harmonic control of the Class-F−1 harmonic network. This proposed PA yields a peak power-added efficiency (PAE) of 47.8%, which is one of the highest when compared to previously reported integrated microwave/millimeter-wave PAs in CMOS and SiGe technologies. The amplifier shows a saturated output power of 14.4 dBm along with an overall gain of 13.8 dB.
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    Novel digital VLSI implementation of data encryption algorithm using nano-metric CMOS technology : a thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Engineering at Massey University, Auckland, New Zealand
    (Massey University, 2013) Ahmad, Nabihah Nornabihah
    Implementations of the Advanced Encryption Standard (AES) have rapidly grown in various applications including telecommunications, finance and networks that require a low power consumption and low cost design. Presented in this thesis is a new 8-bit stream cipher architecture core for an application specific integrated circuit AES crypto-processor. The chip area and power are optimised along with high throughput by employing circuit-level techniques, resource sharing and low supply voltage. The proposed design includes a novel S-box/ InvS-box, MixColumn/ InvMixColumn and ShiftRow/ InvShiftRow with a novel low power Exclusive OR (XOR) gate applied to all sub systems to minimise the power consumption. It is implemented in a 130nm CMOS process and supports both encryption and decryption in Electronic Codebook Mode (EBC) using 128-bit keys with a throughput of 0.05Gbit/s (at 100MHz clock). This design utilises 3152 gate equivalents, including an on-the-fly key scheduling unit along with 4.23μW/MHz power consumption. The area of the chip is 640μm×325μm (0.208 square mm), excluding the bonding pads. Compared to other 8-bit implementations, the proposed design achieves a smaller chip size along with higher throughput and lower power dissipation. This thesis also describes a new fault detection scheme for S-box/ InvS-box that is parity prediction based to protect the key from fault attacks.
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    VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011
    (Massey University, 2011) Khurram, Muhammad
    The wide operating bandwidth of the ultra-wideband (UWB) signal leads to new circuit design challenges and methodologies. Similar to any other RF system, the most critical component of the UWB receiver is the low noise amplifier (LNA). Contrary to the narrowband LNAs, the single-tone assumption is not valid for defining the SNR of an UWB LNA where the input signal encompasses several GHz. Defining the UWB LNA system’s SNR as the matched filter bound (MFB) is an appropriate approach to deduce its noise figure (NF). Using this approach, a mathematical model is proposed to achieve optimal NF, employing the gm-boosted common gate (CG) LNA topology along with a passive noise matching input network. Besides the low noise performance, the other challenges in the design of the UWB LNA include adequate input match and forward power gain with low power dissipation. Considering the superior performance of the gm-boosted CG amplifier topology for UWB, a new single-ended (SE) gm-boosted CG UWB LNA architecture is proposed in this research. In the SE LNA architecture, the power dissipation is further minimized by sharing the bias current between the gm-boosted CG and the active gmboosting amplifier stages in a current-reuse fashion (“piggyback” gm-boosting). The proposed piggyback gm-boosted CG LNA, operating in 3-5 GHz range, is fabricated using 130nm RFCMOS process with adequate results. The noise optimization mathematical model proposed in this thesis is applied to the new piggyback gm-boosted CG LNA architecture by including an intervening noise matching passive network at the input of the LNA. The bandwidth of the noise matched piggyback gm-boosted CG LNA is extended using series peaking technique to the complete UWB band from 3.1 to 10.6 GHz. The proposed full-band noise matched UWB LNA is fabricated in a differential manner using 130nm RFCMOS process and exhibited excellent performance improvements with figure of merit (FOM) of 2.86.
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    Nano-metric optimised CMOS RF receiver front-end components for UHF RFID readers : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Engineering at Massey University, Auckland, New Zealand
    (Massey University, 2011) Li, Jie
    As the capabilities of wireless hand-held devices continue to increase, more pressure is placed on the performance of RF transceiver front-ends. The primary objective of this research is to investigate optimal methods of implementing a receiver front-end with reduced power dissipation, reduced design complexity and minimised cost. This design will be implemented on CMOS technology due to its advantages in system integration and low-cost mass production. This thesis presents the optimisation of a CMOS RF receiver front-end components design for 866 MHz UHF RFID readers. The completed receiver front-end was fabricated on an IBM 130nm CMOS process. Circuit-level techniques were employed to reduce chip size and power consumption while providing enhanced performance. The inclusion of the finite drain-source conductance 𝑔𝑑𝑠 effect improves the nano-metric design optimisation algorithm. Simulated results and experimental data are presented that demonstrate the RF receiver design with low power dissipation and low noise while providing high performance. Low-noise amplifiers using a power-constrained simultaneous noise and input matching (PCSNIM) technique are presented first. In contrast to previously published narrow-band LNA designs, the proposed design methodology includes the finite drain-source conductance of devices, thus achieving simultaneous impedance and minimum noise matching at the very low power drain of 1.6mW from a 1V supply. The LNA delivers a power gain (S21) of 17dB, a reverse isolation (S12) of -34dB and an input power reflection (S11@866 MHz) of -30dB. It has a minimum pass-band NF of around 2dB and a 3rd order input referred intercept point (IIP3) of -16dBm. A low noise mixer is also presented utilising the PCSNIM topology with current bleeding techniques. This design is proposed to replace the conventional Gilbert cell mixer that usually exhibits a high noise figure. The proposed mixer has demonstrated the ability to scale to the targeted 130nm process and meets design requirement at the required operating frequency. It has a power conversion gain of 14.5dB, DSB noise figure of 8.7dB DSB and an IIP3 of -5.1dBM. The mixer core itself only consumes 6mW from a 1.2V supply and the complete test circuit consumes 10mW with a balun at each port. Finally, a voltage controlled oscillator (VCO) is presented. A quadrature VCO (QVCO) structure is selected to overcome the image rejection issue. Since the main goal for this work is to design a low power receiver front-end, a folded-cascode topology is employed to enable the QVCO to operate under 1V power supply. The proposed VCO has a phase noise of -140dBc/Hz at 3-MHz offset from the carrier with only 5mW of power dissipation. This gives a FoM value of -181dBc/Hz that compares favourably to recently published designs.