Novel circuit design for CMOS analog beamformer chip : Doctor of Philosophy in Electronics Engineering at Massey University, Auckland. EMBARGOED until 10 September 2027.
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2023-09-21
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Massey University
Embargoed until 10 September 2027
Embargoed until 10 September 2027
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Abstract
The concept of Beamformer has been around since 1906. They were originally studied for directive communication but later due to their several properties such as beam steering, multiple beams scanning they were incorporated with radar systems during World War II. For future 5G communication, in order to achieve high speed and high bandwidth frequency bands in GHz range are being analysed and beamformers are proving themselves very useful by providing high transmitting power and high signal to noise ratio at mm-wave frequencies. At high frequencies as the antenna size reduces and it becomes possible to put multiple antennas in small space for beamforming. Moreover, as the number of elements is increased, the overall gain of the system increases which compensates for the path loss present at mm-wave frequencies. But increase in number of the elements increases the overall cost and power consumption of the beamformer. There are several architectures present in the literature to design the beamformer. But power consumption, and cost of the system is still an issue for beamformer design for applications where high cost is an issue. This research work is focused on reducing the overall cost of a beamformer. The cost in integrated circuit (IC) design refers to DC power, silicon area and external control required to use the IC.
Phase shifter is the vital part of a beamformer which provides the relative phase shift between each element of a beamformer in order to create a beam and then steer it in desired direction. The cost and size of the phase shifter affects the overall cost of the beamformer as it takes around 40% of the total cost. In this work two new active analog phase shifters are proposed. The proposed phase shifters are based on cartesian combining method where in-phase and quadrature signals are scaled and added together so that a desired phase can be achieved at the output. The first phase shifter is proposed for the frequency band of 25 GHz – 30 GHz. The proposed phase shifter incorporates a closed loop error tuning circuit in the in-phase quadrature signal generator. This approach reduces the I/Q amplitude and phase imbalance of the I/Q generator below 0.3 dB and 1.1° respectively for a wide bandwidth of 5 GHz. Moreover, the active phase shifter consumes only 22.8 mV from a 1V supply.
The second phase shifter incorporates a novel variable gain amplifier (VGA) which improves the overall input referred 1-dB compression point (IP1dB) of the phase shifter while maintaining comparably low DC power consumption. The proposed VGA is designed using folded topology with dual differential architecture. The resulting phase shifter has the lowest IP1dB of +2.5 dBm at the center frequency of 8 GHz which is very high compared to most of the phase shifters present in the literature. The designed phase shifter consumes 18.9 mW core power (I/Q generator, VGA) from 1.8 V supply.
Limited scan beamformer is selected as cost-effective approach to design a beamformer in this work. Limited scan beamformer reduces the overall cost by reducing the number of variable phase shifters used in a beamformer while achieving an optimum scanning range. There are three main limited scan beamformer architectures (OSA, NOSA and feed network with single phase shifter) are studied in detail and their radiation pattern is plotted for comparative analysis. Next a novel 7-channel active beamformer transmitter is proposed with a novel feed network. The novel feed network allows to use only three variable phase shifters for a 7- channel beamformer at a center frequency of 9 GHz. This reduces the complexity and the overall cost of the beamformer. The beamformer is designed using TSMC 180nm CMOS process. The proposed beamformer consumes a total of 523.71 mW of the power which equates to 74.8 mW per channel. A MATLAB code is used to plot the radiation pattern of the beamformer for different scan angles. The proposed beamformer has a scanning range of around ±19° which is very high compared to most of the limited scan beamformers in the literature while maintaining a side lobe level (SLL) of -7dB and below.
The phase shifters and beamformer proposed in this work have simple analog architectures and control circuitry.
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Keywords
Analog CMOS integrated circuits, Beamforming, Mathematical models, Phase shifters, Antenna arrays, analog beamformer, VGA, limited scan beamformer