Union-Retire for Connected Components Analysis on FPGA.

dc.citation.issue4
dc.citation.volume8
dc.contributor.authorBailey DG
dc.contributor.authorKlaiber MJ
dc.contributor.editorJuan GB
dc.coverage.spatialSwitzerland
dc.date.accessioned2024-04-08T02:08:26Z
dc.date.accessioned2024-07-25T06:46:11Z
dc.date.available2022-03-24
dc.date.available2024-04-08T02:08:26Z
dc.date.available2024-07-25T06:46:11Z
dc.date.issued2022-03-24
dc.description.abstractThe Union-Retire CCA (UR-CCA) algorithm started a new paradigm for connected components analysis. Instead of using directed tree structures, UR-CCA focuses on connectivity. This algorithmic change leads to a reduction in required memory, with no end-of-row processing overhead. In this paper we describe a hardware architecture based on UR-CCA and its realisation on an FPGA. The memory bandwidth and pipelining challenges of hardware UR-CCA are analysed and resolved. It is shown that up to 36% of memory resources can be saved using the proposed architecture. This translates directly to a smaller device for an FPGA implementation.
dc.description.confidentialfalse
dc.edition.editionApril 2022
dc.format.pagination89-
dc.identifier.author-urlhttps://www.ncbi.nlm.nih.gov/pubmed/35448215
dc.identifier.citationBailey DG, Klaiber MJ. (2022). Union-Retire for Connected Components Analysis on FPGA.. J Imaging. 8. 4. (pp. 89-).
dc.identifier.doi10.3390/jimaging8040089
dc.identifier.eissn2313-433X
dc.identifier.elements-typejournal-article
dc.identifier.issn2313-433X
dc.identifier.number89
dc.identifier.piijimaging8040089
dc.identifier.urihttps://mro.massey.ac.nz/handle/10179/70831
dc.languageeng
dc.publisherMDPI (Basel, Switzerland)
dc.publisher.urihttps://www.mdpi.com/2313-433X/8/4/89
dc.relation.isPartOfJ Imaging
dc.rights(c) 2022 The Author/s
dc.rightsCC BY 4.0
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/
dc.subjectFPGA
dc.subjectconnected components
dc.subjectfeature extraction
dc.subjectpipelined
dc.subjectunion-find
dc.titleUnion-Retire for Connected Components Analysis on FPGA.
dc.typeJournal article
pubs.elements-id452768
pubs.organisational-groupOther
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