A logic-level simulation of the ATMSWITCH : a thesis presented in partial fulfilment of the requirements for the degree of Master of Science in Computer Science at Massey University

Simple item page
dc.contributor.authorYan, Bo
dc.date.accessioned2018-02-28T22:02:25Z
dc.date.available2018-02-28T22:02:25Z
dc.date.issued1998
dc.description.abstractATM networks are intended to provide a "one-size-fits-all" solution to a variety of data communication needs, from low speed, delay-insensitive to high-speed, delay-intolerant. The basic ATM protocol certainly delivers traffic within this broad range, but it does not address the quality of service requirements associated with the various type of traffic. The ATMSW1TCH is designed to use two different mechanisms to provide the quality of service for the various type of traffic. It treats the cells according to their connected virtual channel type and services them as predefined scheme. The ATMSWITCH architecture is a shared-memory and output buffer strategy switch. The switch has been designed much of buffer location and identification can occur in parallel with the 12ns read/write cycle time required to buffer the cell data. The problem is essentially one of design circuitry so that buffer location and identification are as short as possible. The present project has therefore been intended to measure the number of clock cycles required to perform the buffer maintenance activities, and to determine whether the logic speed required to fit this number of clock cycles into the 12ns window is feasible using current technology. The simulated result and timing analysis shows that 10 clock cycles are required during 12ns buffer read and write time, and a reasonable clock speed is 1.2ns per clock cycle.en_US
dc.identifier.urihttp://hdl.handle.net/10179/12860
dc.language.isoenen_US
dc.publisherMassey Universityen_US
dc.rightsThe Authoren_US
dc.subjectComputer simulationen_US
dc.subjectAsynchronous transfer modeen_US
dc.subjectIntegrated services digital networksen_US
dc.subjectBroadband communication systemsen_US
dc.titleA logic-level simulation of the ATMSWITCH : a thesis presented in partial fulfilment of the requirements for the degree of Master of Science in Computer Science at Massey Universityen_US
dc.typeThesisen_US
massey.contributor.authorYan, Bo
thesis.degree.disciplineComputer Scienceen_US
thesis.degree.grantorMassey Universityen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Science (M. Sc.)en_US
Files
Original bundle
Now showing 1 - 2 of 2
Thumbnail Image
Name:
01_front.pdf
Size:
2.25 MB
Format:
Adobe Portable Document Format
Description:
Download
Thumbnail Image
Name:
02_whole.pdf
Size:
25.55 MB
Format:
Adobe Portable Document Format
Description:
Download
License bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
license.txt
Size:
3.32 KB
Format:
Item-specific license agreed upon to submission
Description:
Download
Collections
Theses and Dissertations