|dc.description.abstract||In modern point to point microwave radio systems used to backhaul cellular
voice and data traffic, quadrature amplitude modulation (QAM) is the norm.
These systems require a highly linear power amplifier which is expensive and
has relatively low power efficiency. Recently, continuous phase modulation
(CPM) has been deployed in this market. The CPM transmitted waveform has
a constant envelope and so a non-linear RF power amplifier can be used. This
significantly reduces cost and improves power efficiency.
Two important disadvantages of CPM are receiver complexity and inferior
spectral efficiency compared to QAM. This thesis demonstrates a 50% spectral
efficiency improvement over an existing CPM configuration without loss of
detection efficiency. This is achieved by moving to coherent demodulation and
extending the duration of the CPM phase pulse to 3 symbol periods.
This new CPM configuration of h=1/4, M=4, L=3, is evaluated against ETSI
requirements for a 28 MHz channel carrying 24 E1 circuits. Simulation of the
receiver floating point model demonstrates all requirements are met. The detection
efficiency requirement is exceeded by 4.7 dB. Carrier recovery, phase
and timing synchronisation are assumed to be ideal.
The 50% increased symbol rate, coherent reception and a longer smoother
phase pulse, conspire to increase receiver complexity substantially. The Viterbi
algorithm is used to perform maximum-likelihood detection resulting in a 128
state trellis. This application has a stringent cost requirement that limits the
implementation target to a Field Programmable Gate Array (FPGA) costing
less than US$30. To demonstrate this demanding cost target is met, the two
most computationally expensive receiver functions, the branch metric unit and
path metric processing unit, are implemented in VHDL and targeted to a Xilinx
Spartan 3A-DSP 1800 FPGA. The implementation uses 67% of the available
logic resources, thus meeting the cost requirement.
The branch metric unit is implemented using a distributed arithmetic technique
that performs the equivalent of 27.6 giga-multiplies/s, consuming only
23% of the available FPGA logic cells. This is very efficient compared to a conventional
approach using all the FPGA’s embedded multipliers which combined
can only achieve 21 giga-multiplies/s.
The Viterbi path metric processing unit is implemented using a more conventional
state-parallel architecture. To reduce state metric routing complexity,
states are grouped into radix-4 units comprising dual add-compare-select
(ACS) units. By utilising a spare cycle in the deep ACS pipeline, each ACS
unit processes two output state metrics, thus halving the number of ACS units
required. This implementation uses 44% of the available FPGA resources and
meets timing at 204.5 MHz, exceeding the throughput requirement of 54 Mbit/s.||en_US