Integrated power amplifier and antenna-on-chip for 5G communication applications : thesis by publications presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Engineering, Massey University, Auckland, New Zealand

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dc.confidentialEmbargo : Noen_US
dc.contributor.advisorAlam, Fakhrul
dc.contributor.authorAli, Syed Muhammad Ammar
dc.date.accessioned2023-10-30T03:16:08Z
dc.date.accessioned2024-01-08T02:12:24Z
dc.date.available2023-10-30T03:16:08Z
dc.date.available2024-01-08T02:12:24Z
dc.date.issued2023
dc.descriptionChapters 4 and 5 are reproduced under a Creative Commons Attribution 4.0 International license (CC BY 4.0 Deed).en_US
dc.descriptionen_US
dc.description.abstractWith the advent of 5G cellular networks, there is a crucial requirement for wireless hardware operable at microwave and millimeter-wave (mmW) frequencies. Two significant elements of wireless hardware are Power Amplifier (PA) and Antenna. An integrated power amplifier designed for 5G communications is expected to offer maximum performance in terms of efficiency, output power, and/or gain. An On-Chip Antenna design would require features like simple geometry, a small form factor, free from the risk of micro-fracture, and cost-effectiveness. Among different classes of PAs, the Class-F-1 amplifier is selected because it offers relatively better output power and efficiency. Different techniques are utilized in this work to enhance the performance parameters of the Class-F-1 PA, designed at the 5G-millimeterwave frequency of 38-GHz. In order to achieve high gain, a two-stage topology of Class-F-1 PA is employed. For the purpose of obtaining high output power, a stacking structure is established in the final stage of the two-stage topology. Class-F-1-based parasitic-aware harmonic-control loading is employed to improve the efficiency of the power amplifier. Therefore, a two-stage Class-F-1 power amplifier with a double-stacked configuration is designed and fabricated. GlobalFoundries 8HP 130nm SiGe-BiCMOS process technology is utilized for realizing the integrated mmW power amplifier. A Figure of Merit (FoM) is calculated for comparing the performance of the designed power amplifier with other mmW amplifiers reported in the literature. It is observed that the proposed two-stage double-stacked Class-F-1 PA shows comparatively the highest FoM (69.68) achieved so far in state-of-the-art silicon-based Class F/F-1 power amplifiers. Another integrated Class-F-1 power amplifier is proposed at a new unlicensed 5G-microwave frequency of 6-GHz. The PA is designed to achieve very high power-efficiency. The amplifier employs a “single-transistor” design in 65-nm standard CMOS process technology. The PA is loaded with a Class-F-1 harmonic-control network, employing a new parasitic-aware topology deduced using a novel iterative-algorithm. The proposed algorithm starts from a specific reference value and quickly converges towards the solution. A dual-purpose output-matching circuit is employed in the design. The output-matching circuit not only matches the output impedance to 50-Ω but also reinforces the Class-F-1 harmonic network in controlling the harmonics efficiently. The proposed amplifier offers a peak power-added-efficiency (PAE) of 47.8% which is one of the highest when compared with previously reported microwave/millimeterwave PAs in CMOS and SiGe process technologies. Besides power-amplifiers, another essential part of this research is On-Chip Antenna (OCA). As millimeterwave frequencies exhibit relatively smaller wavelengths, it becomes feasible to design an antenna on a microchip using standard CMOS processes. As compared to Off-Chip Antennas, the On-Chip Antennas offer a high level of integration with RF-front-end circuitry, as well as an external interconnect-free interface and low fabrication cost. An On-Chip Planar-Inverted-F Antenna (PIFA) in TSMC 180-nm CMOS is designed to radiate at the 5G-millimeterwave frequency of 38-GHz. A PIFA is selected because it offers simple geometry, small form factor, design flexibility, and robustness. An Ultra-Thick Metal (UTM) layer in 180-nm CMOS is utilized to implement the antenna structure on the chip. To achieve better radiation performance, the OCA is positioned close to the edge of the microchip. The measurements are conducted after placing the fabricated OCA over a 3D-printed plastic-slab to minimize the reflections from the metallic-chuck of the probe-station. The fabricated OCA delivered an antenna-gain of 0.7-dBi at the millimeterwave center-frequency of 38-GHz.en_US
dc.identifier.urihttps://mro.massey.ac.nz/handle/10179/69289
dc.publisherMassey Universityen_US
dc.rightsThe Authoren_US
dc.rightsCopyright is owned by the Author of the thesis. Permission is given for a copy to be downloaded by an individual for the purpose of research and private study only. The thesis may not be reproduced elsewhere without the permission of the Author.en
dc.subject5G mobile communication systemsen
dc.subjectEquipment and suppliesen
dc.subjectMicrowave communication systemsen
dc.subjectAmplifiers (Electronics)en
dc.subjectMicrowave antennasen
dc.subjectIntegrated circuitsen
dc.subject.anzsrc400601 Antennas and propagationen
dc.titleIntegrated power amplifier and antenna-on-chip for 5G communication applications : thesis by publications presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Engineering, Massey University, Auckland, New Zealanden_US
dc.typeThesisen_US
massey.contributor.authorAli, Syed Muhammad Ammaren_US
thesis.degree.disciplineMicroelectronicsen_US
thesis.degree.grantorMassey Universityen_US
thesis.degree.levelDoctoralen_US
thesis.degree.nameDoctor of Philosophy (PhD)en_US
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