Designing application-specific processors for image processing : a thesis presented in partial fulfilment of the requirements for the degree of Master of Science in Computer Science, Massey University, Palmerston North, New Zealand
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Date
2008
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Massey University
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Abstract
Implementing a real-time image-processing algorithm on a serial
processor is difficult to achieve because such a processor cannot cope with the
volume of data in the low-level operations. However, a parallel implementation,
required to meet timing constraints for the low-level operations, results in low
resource utilisation when implementing the high-level operations. These factors
suggested a combination of parallel hardware, for the low-level operations, and
a serial processor, for the high-level operations, for implementing a high-level
image-processing algorithm.
Several types of serial processors were available. A general-purpose
processor requires an extensive instruction set to be able to execute any
arbitrary algorithm resulting in a relatively complex instruction decoder and
possibly extra FUs. An application-specific processor, which was considered in
this research, implements enough FUs to execute a given algorithm and
implements a simpler, and more efficient, instruction decoder. In addition, an
algorithms behaviour on a processor could be represented in either hardware
(i.e. hardwired logic), which limits the ability to modify the algorithm behaviour
of a processor, or “software” (i.e. programmable logic), which enables external
sources to specify the algorithm behaviour.
This research investigated hardware- and software- controlled
application-specific serial processors for the implementation of high-level
image-processing algorithms and compared these against parallel hardware and
general-purpose serial processors. It was found that application-specific
processors are easily able to meet the timing constraints imposed by real-time
high-level image processing. In addition, the software-controlled processors had
additional flexibility, a performance penalty of 9.9% and 36.9% and
inconclusive footprint savings (and costs) when compared to hardwarecontrolled
processors.
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Keywords
Serial processor, Algorithms, High-level image processing