Designing application-specific processors for image processing : a thesis presented in partial fulfilment of the requirements for the degree of Master of Science in Computer Science, Massey University, Palmerston North, New Zealand
dc.contributor.author | Bishell, Aaron | |
dc.date.accessioned | 2009-10-06T22:53:27Z | |
dc.date.available | NO_RESTRICTION | en_US |
dc.date.available | 2009-10-06T22:53:27Z | |
dc.date.issued | 2008 | |
dc.description.abstract | Implementing a real-time image-processing algorithm on a serial processor is difficult to achieve because such a processor cannot cope with the volume of data in the low-level operations. However, a parallel implementation, required to meet timing constraints for the low-level operations, results in low resource utilisation when implementing the high-level operations. These factors suggested a combination of parallel hardware, for the low-level operations, and a serial processor, for the high-level operations, for implementing a high-level image-processing algorithm. Several types of serial processors were available. A general-purpose processor requires an extensive instruction set to be able to execute any arbitrary algorithm resulting in a relatively complex instruction decoder and possibly extra FUs. An application-specific processor, which was considered in this research, implements enough FUs to execute a given algorithm and implements a simpler, and more efficient, instruction decoder. In addition, an algorithms behaviour on a processor could be represented in either hardware (i.e. hardwired logic), which limits the ability to modify the algorithm behaviour of a processor, or “software” (i.e. programmable logic), which enables external sources to specify the algorithm behaviour. This research investigated hardware- and software- controlled application-specific serial processors for the implementation of high-level image-processing algorithms and compared these against parallel hardware and general-purpose serial processors. It was found that application-specific processors are easily able to meet the timing constraints imposed by real-time high-level image processing. In addition, the software-controlled processors had additional flexibility, a performance penalty of 9.9% and 36.9% and inconclusive footprint savings (and costs) when compared to hardwarecontrolled processors. | en_US |
dc.identifier.uri | http://hdl.handle.net/10179/1024 | |
dc.language.iso | en | en_US |
dc.publisher | Massey University | en_US |
dc.rights | The Author | en_US |
dc.subject | Serial processor | en_US |
dc.subject | Algorithms | en_US |
dc.subject | High-level image processing | en_US |
dc.subject.other | Fields of Research::280000 Information, Computing and Communication Sciences::280200 Artificial Intelligence and Signal and Image Processing::280203 Image processing | en_US |
dc.title | Designing application-specific processors for image processing : a thesis presented in partial fulfilment of the requirements for the degree of Master of Science in Computer Science, Massey University, Palmerston North, New Zealand | en_US |
dc.type | Thesis | en_US |
massey.contributor.author | Bishell, Aaron | |
thesis.degree.discipline | Computer Science | en_US |
thesis.degree.grantor | Massey University | en_US |
thesis.degree.level | Masters | en_US |
thesis.degree.name | Master of Science (M. Sc.) | en_US |
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