Novel digital VLSI implementation of data encryption algorithm using nano-metric CMOS technology : a thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Engineering at Massey University, Auckland, New Zealand

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dc.contributor.authorAhmad, Nabihah Nornabihah
dc.date.accessioned2014-04-30T04:03:18Z
dc.date.available2014-04-30T04:03:18Z
dc.date.issued2013
dc.descriptionThe following articles were removed due to copyright restrictions: Ahmad, N., Hasan, R. (2013) "A 0.8 V 0.23 nW 1.5 ns full-swing pass-transistor XOR gate in 130 nm CMOS", Active and passive electronic components, 1-6; Ahmad, N., Rezaul Hasan, S.M., (2012) "Efficient integrated AES crypto-processor architecture for 8-bit stream cipher", Electronic Letters, IET, 48:23, 1456-1457; Ahmad, N., Rezaul Hasan, S.M. (2013) "Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate", Integration, the VLSI Journal, 46:4, 333-345; Ahmad, N., Hasan, R. (2012) "Topology of 2 input subnanowatt XOR gate in 65nm CMOS technology," in Proceedings of IEEE International Conference on Semiconductor Electronics 2012 (ICSE2012), Sept. 19-21, Kuala Lumpur, Malaysia, 597-599; Ahmad, N., Rezaul Hasan, S.M. (2011) "Decomposition method for AES Mix Column and Inv Mix Column VLSI architecture optimization", Proceedings 18th Electronics New Zealand Conference, Palmerston North, New Zealand, 91-94; Ahmad, N., Hasan, R. (2011) "A new design of XOR-XNOR gates for low power application", Proceedings 2011 IEEE International Conference on Electronic Devices, Systems and Applications (ICEDSA), 25-27 Apr, Kuala Lumpur, Malaysia, 45-49.en
dc.description.abstractImplementations of the Advanced Encryption Standard (AES) have rapidly grown in various applications including telecommunications, finance and networks that require a low power consumption and low cost design. Presented in this thesis is a new 8-bit stream cipher architecture core for an application specific integrated circuit AES crypto-processor. The chip area and power are optimised along with high throughput by employing circuit-level techniques, resource sharing and low supply voltage. The proposed design includes a novel S-box/ InvS-box, MixColumn/ InvMixColumn and ShiftRow/ InvShiftRow with a novel low power Exclusive OR (XOR) gate applied to all sub systems to minimise the power consumption. It is implemented in a 130nm CMOS process and supports both encryption and decryption in Electronic Codebook Mode (EBC) using 128-bit keys with a throughput of 0.05Gbit/s (at 100MHz clock). This design utilises 3152 gate equivalents, including an on-the-fly key scheduling unit along with 4.23μW/MHz power consumption. The area of the chip is 640μm×325μm (0.208 square mm), excluding the bonding pads. Compared to other 8-bit implementations, the proposed design achieves a smaller chip size along with higher throughput and lower power dissipation. This thesis also describes a new fault detection scheme for S-box/ InvS-box that is parity prediction based to protect the key from fault attacks.en
dc.identifier.urihttp://hdl.handle.net/10179/5308
dc.language.isoenen
dc.publisherMassey Universityen_US
dc.rightsThe Authoren_US
dc.subjectAdvanced Encryption Standard (AES)en
dc.subjectData encryptionen
dc.subjectIntegrated circuitsen
dc.subjectVery large scale integration (VLSI)en
dc.subjectCMOSen
dc.subjectCrypto-processoren
dc.subjectPower consumption (Computing)en
dc.subjectComputer algorithmsen
dc.titleNovel digital VLSI implementation of data encryption algorithm using nano-metric CMOS technology : a thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Engineering at Massey University, Auckland, New Zealanden
dc.typeThesisen
massey.contributor.authorAhmad, Nabihahen
thesis.degree.disciplineEngineeringen
thesis.degree.grantorMassey Universityen
thesis.degree.levelDoctoralen
thesis.degree.nameDoctor of Philosophy (Ph.D.)en
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