Nano-metric optimised CMOS RF receiver front-end components for UHF RFID readers : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Engineering at Massey University, Auckland, New Zealand
Loading...
Files
Date
2011
DOI
Open Access Location
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
Massey University
Rights
The Author
Abstract
As the capabilities of wireless hand-held devices continue to increase, more pressure is placed on the performance of RF transceiver front-ends. The primary objective of this research is to investigate optimal methods of implementing a receiver front-end with reduced power dissipation, reduced design complexity and minimised cost. This design will be implemented on CMOS technology due to its advantages in system integration and low-cost mass production.
This thesis presents the optimisation of a CMOS RF receiver front-end components design for 866 MHz UHF RFID readers. The completed receiver front-end was fabricated on an IBM 130nm CMOS process. Circuit-level techniques were employed to reduce chip size and power consumption while providing enhanced performance. The inclusion of the finite drain-source conductance 𝑔𝑑𝑠 effect improves the nano-metric design optimisation algorithm. Simulated results and experimental data are presented that demonstrate the RF receiver design with low power dissipation and low noise while providing high performance.
Low-noise amplifiers using a power-constrained simultaneous noise and input matching (PCSNIM) technique are presented first. In contrast to previously published narrow-band LNA designs, the proposed design methodology includes the finite drain-source conductance of devices, thus achieving simultaneous impedance and minimum noise matching at the very low power drain of 1.6mW from a 1V supply. The LNA delivers a power gain (S21) of 17dB, a reverse isolation (S12) of -34dB and an input power
reflection (S11@866 MHz) of -30dB. It has a minimum pass-band NF of around 2dB and a 3rd order input referred intercept point (IIP3) of -16dBm. A low noise mixer is also presented utilising the PCSNIM topology with current bleeding techniques. This design is proposed to replace the conventional Gilbert cell mixer that usually exhibits a high noise figure. The proposed mixer has demonstrated the ability to scale to the targeted 130nm process and meets design requirement at the required operating frequency. It has a power conversion gain of 14.5dB, DSB noise figure of 8.7dB DSB and an IIP3 of -5.1dBM. The mixer core itself only consumes 6mW from a 1.2V supply and the complete test circuit consumes 10mW with a balun at each port. Finally, a voltage controlled oscillator (VCO) is presented. A quadrature VCO (QVCO) structure is selected to overcome the image rejection issue. Since the main goal for this work is to design a low power receiver front-end, a folded-cascode topology is employed to enable the QVCO to operate under 1V power supply. The proposed VCO has a phase noise of -140dBc/Hz at 3-MHz offset from the carrier with only 5mW of power dissipation. This gives a FoM value of -181dBc/Hz that compares favourably to recently published designs.
Description
Keywords
RFID, Radio frequency identification systems, CMOS, RF transceiver, Low noise amplifiers