VLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011

dc.contributor.authorKhurram, Muhammad
dc.date.accessioned2012-08-15T04:15:27Z
dc.date.available2012-08-15T04:15:27Z
dc.date.issued2011
dc.description.abstractThe wide operating bandwidth of the ultra-wideband (UWB) signal leads to new circuit design challenges and methodologies. Similar to any other RF system, the most critical component of the UWB receiver is the low noise amplifier (LNA). Contrary to the narrowband LNAs, the single-tone assumption is not valid for defining the SNR of an UWB LNA where the input signal encompasses several GHz. Defining the UWB LNA system’s SNR as the matched filter bound (MFB) is an appropriate approach to deduce its noise figure (NF). Using this approach, a mathematical model is proposed to achieve optimal NF, employing the gm-boosted common gate (CG) LNA topology along with a passive noise matching input network. Besides the low noise performance, the other challenges in the design of the UWB LNA include adequate input match and forward power gain with low power dissipation. Considering the superior performance of the gm-boosted CG amplifier topology for UWB, a new single-ended (SE) gm-boosted CG UWB LNA architecture is proposed in this research. In the SE LNA architecture, the power dissipation is further minimized by sharing the bias current between the gm-boosted CG and the active gmboosting amplifier stages in a current-reuse fashion (“piggyback” gm-boosting). The proposed piggyback gm-boosted CG LNA, operating in 3-5 GHz range, is fabricated using 130nm RFCMOS process with adequate results. The noise optimization mathematical model proposed in this thesis is applied to the new piggyback gm-boosted CG LNA architecture by including an intervening noise matching passive network at the input of the LNA. The bandwidth of the noise matched piggyback gm-boosted CG LNA is extended using series peaking technique to the complete UWB band from 3.1 to 10.6 GHz. The proposed full-band noise matched UWB LNA is fabricated in a differential manner using 130nm RFCMOS process and exhibited excellent performance improvements with figure of merit (FOM) of 2.86.en
dc.identifier.urihttp://hdl.handle.net/10179/3701
dc.language.isoenen
dc.publisherMassey Universityen_US
dc.rightsThe Authoren_US
dc.subjectIntegrated circuitsen
dc.subjectVery large scale integrationen
dc.subjectComputer-aided designen
dc.subjectVLSIen
dc.subjectCMOSen
dc.titleVLSI design, fabrication and testing of an ultra-wideband low noise amplifier microchip using nanometric CMOS technology : [a thesis presented in partial fulfilment of the requirements for the degree of] Doctor of Philosophy in Engineering, Integrated Circuit Design at School of Engineering and Technology of Massey Univeristy [i.e. University], Albany, November 2011en
dc.typeThesisen
massey.contributor.authorKhurram, Muhammaden
thesis.degree.disciplineEngineering, Integrated Circuit Designen
thesis.degree.grantorMassey Universityen
thesis.degree.levelDoctoralen
thesis.degree.nameDoctor of Philosophy (Ph.D.)en
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