A two-dimensional extensible bus technology and protocol for VLSI processor core : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Computer and Electronic Engineering at School of Engineering and Advanced Technology, Massey University, Albany, New Zealand
| dc.contributor.author | Loke, Chun Eng | |
| dc.date.accessioned | 2012-06-22T01:50:55Z | |
| dc.date.available | 2012-06-22T01:50:55Z | |
| dc.date.issued | 2011 | |
| dc.description.abstract | Intellectual property (IP) core design modularity and reuse in Very-Large-Scale-Integration (VLSI) silicon have been the key focus areas in design productivity improvement in order to shorten product development lead time as well as minimize design error on new product [11]. The System-On-Chip (SoC) design approach has been adopted in microprocessor design flow with many functional blocks reuse in silicon. SoC has the advantage of cost efficiency and higher fabrication yield. The fundamental building block of SoC is the interconnection of intellectual property (IP) core through a shared bus to establish an on-chip communication. As IP core integration is severely constraint by silicon wafer sizes (cost per die), the right level of integration is never an easy decision. System-in-Package (SiP) addresses this drawback with package level IP core integration. However, SiP has the drawback of lower fabrication yield which results in higher manufacturing cost [6]. In order to address these issues, a new level of integration has been suggested in order to reduce the drawbacks of SiP and SoC approaches. This new integration methodology is also known as System-in-System (SiS) which emulates SoC and SiP at the system level. The thesis contains a detailed treatment on the processor architecture and SoC used. The design methodologies have been discussed too. The thesis also contains treatment on the verification methodologies and technologies that are used in design validation. Research includes the design of two dimensional XBUS system for external IP core integration on SoC. The thesis proposed a system level bus for IP integration through the XBUS. As there are multiple ways of integrating IP core at the system level, the XBUS is limited to two channels (hence two dimensional) in order to simplify implementation complexities. Based on experimental results, the proposed method can be introduced as a very promising method for the design of SoC and various other high-performance computer systems. | en |
| dc.identifier.uri | http://hdl.handle.net/10179/3511 | |
| dc.language.iso | en | en |
| dc.publisher | Massey University | en_US |
| dc.rights | The Author | en_US |
| dc.subject | Integrated circuits | en |
| dc.subject | Systems on a chip | en |
| dc.subject | Two-dimensional extensible bus technology | en |
| dc.subject | VLSI processor core | en |
| dc.title | A two-dimensional extensible bus technology and protocol for VLSI processor core : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Computer and Electronic Engineering at School of Engineering and Advanced Technology, Massey University, Albany, New Zealand | en |
| dc.type | Thesis | en |
| massey.contributor.author | Loke, Chun Eng | en |
| thesis.degree.discipline | Computer and Electronic Engineering | en |
| thesis.degree.grantor | Massey University | en |
| thesis.degree.level | Masters | en |
| thesis.degree.name | Master of Engineering (M.E.) | en |
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